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1 for more information www.linear.com/LTC3874 load current (a) 0 70 efficiency (%) power loss (w) 75 80 85 90 100 95 0 4 2 6 8 10 14 12 10 20 50 30 60 40 3874 ta01b efficiency power loss 1.5m 0.32m 1.5m 0.32m v in = 12v v out = 1.8v ccm typical application features description polyphase step-down synchronous slave controller with sub-milliohm dcr sensing the lt c ? 3874 is a dual polyphase ? current mode synchro - nous step -down slave controller. it enables high current, multi-phase applications when paired with a companion master controller by extending the phase count. compat - ible master controllers include the ltc3866, ltc3875 and ltc3774. the LTC3874 employs a unique architecture that enhances the signal-to-noise ratio of the current sense signal, allowing the use of sub-milliohm dc resistance power inductors to maximize efficiency while reduc - ing switching jitter. its peak current mode architecture allows for accurate phase to phase current sharing even for dynamic loads. effectively working with a master controller, the LTC3874 supports all the programmable features as well as fault protection. the constant operating frequency can be synchronized to an external clock or linearly programmed from 250khz to 1mhz. l, lt , lt c , lt m , linear technology, the linear logo, polyphase and burst mode are registered trademarks of linear technology corporation. all other trademarks are the property of their respective owners. protected by u.s. patents, including 5481178, 5705919, 5929620, 6100678, 6144194, 6177787, 6304066, 6580258. applications n phase extender for high phase count voltage rails n accurate phase-to-phase current sharing n sub-milliohm dcr current sensing n phase-lockable fixed frequency 250khz to 1mhz n immediate response to master ic's fault n up to 12 phase operation n wide v in range: 4.5v to 38v n v out up to 5.5v n proprietary current mode control loop n programmable ccm/dcm operation n programmable phase shift control n dual n-channel mosfet gate drivers n 28-lead (4mm 5mm) qfn package n high current distributed power systems n telecom, datacom, and storage systems n intelligent energy efficient power regulation dual phase efficiency and power loss vs output current, sub-milliohm dcr vs traditional dcr phasmd lowdcr extv cc freq ilim boost0 tg0 sw0 bg0 LTC3874 bg1 sw1 tg1 gnd run0 sync run1 fault0 fault1 0.33h (0.32m dcr) 0.33h (0.32m dcr) run0 gpio0 gpio1 run1 sync i th0 i th1 v sense0 + master controller i sense1 + i sense1 ? i sense0 + i sense0 ? i th0 i th1 v sense1 + 470f 2 v out 1.8v 120a v in v in intv cc pgood0 pgood1 mode0 mode1 boost1 + 470f 2 + 90k 931 931 0.1f 0.1f 0.22f 4.7f 0.22f 3874 ta02 ltc 3874 3874f
2 for more information www.linear.com/LTC3874 pin configuration absolute maximum ratings v in ............................................................. ?0. 3 v to 40 v boost 0, boost1 ...................................... ? 0.3 v to 46 v sw 0, sw1 .................................................... ? 5 v to 40 v (boost 0- sw 0), ( boost 1- sw 1) ................. ? 0.3 v to 6v i sense 0 + , i sense 0 C , i sense 1 + , i sense 1 C ... ?0.3 v to intv cc extv cc , intv cc , run 0, run 1 .................... ? 0.3 v to 6v mode 0, mode 1, ilim , lowdcr , phasmd , freq .................................... ? 0.3 v to intvcc sync , fau lt 0 , fau lt 1 , i th 0 , i th 1 ......... ?0.3 v to intvcc intv cc peak output current ................................ 10 0 ma operating junction temperature range ( note 2) .................................................. ? 40 c to 125 c storage temperature range .................. ? 65 c to 150 c (note 1) 9 10 top view 29 gnd ufd package 28-lead (4mm 5mm) plastic qfn 11 12 13 28 27 26 25 24 14 23 6 5 4 3 2 1 mode0 i sense0 + i sense0 ? run0 run1 i sense1 ? i sense1 + mode1 boost0 bg0 v in intv cc extv cc bg1 boost1 sw1 i th0 lowdcr fault0 fault1 tg0 sw0 i th1 freq ilim sync phasmd tg1 7 17 18 19 20 21 22 16 8 15 ja = 43c/w, jc = 3.4c/w exposed pad ( pin 29) is gnd, must be soldered to pcb order information lead free finish tape and reel part marking* package description temperature range LTC3874eufd#pbf LTC3874eufd#trpbf 3874 28-lead (4mm 5mm) plastic qfn C40c to 125c LTC3874iufd#pbf LTC3874iufd#trpbf 3874 28-lead (4mm 5mm) plastic qfn C40c to 125c consult lt c marketing for parts specified with wider operating temperature ranges. *the temperature grade is identified by a label on the shipping container . consult lt c marketing for information on nonstandard lead based finish parts. for more information on lead free part marking, go to: http://www.linear.com/leadfree/ for more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/ 3874f ltc 3874
3 for more information www.linear.com/LTC3874 electrical characteristics symbol parameter conditions min typ max units input voltage v in input voltage range 4.5 38 v v out output voltage range lowdcr = intv cc (note 3) lowdcr = 0v 3.5 5.5 v v i q input dc supply current normal operation shutdown ( note 4) v run0,1 = 3.3v v run0,1 = 0v 4.6 1.8 ma ma v uvlo undervoltage lockout threshold v intvcc falling v intvcc rising 3.5 3.8 v v control loop i isense0,1 i sense pins bias current v isense0,1 < (v intvcc C 3.3v) v isense0,1 > (v intvcc C 3.3v) l l 0.15 1 0.4 3 a a v isense(max) maximum current sense threshold (table 1) ilim = intv cc , lowdcr = intv cc , v isense0,1 = 1.2v, v ith = 2.18v l 26.8 28.8 30.8 mv ilim = 0v, lowdcr = int v cc , v isense0,1 = 1.2v, v ith = 2.18v l 14.5 16 17.5 mv ilim = intv cc , lowdcr = 0v, v isense0,1 = 1.2v, v ith = 2.18v l 65 72 79 mv ilim = 0v, lowdcr = 0v, v isense0,1 = 1.2v, v ith = 2.18v l 33 40 47 mv gate drivers tg r up tg pull-up r ds(on) tg high 2.6 tg r down tg pull-down r ds(on) tg low 1.5 bg r up bg pull-up r ds(on) bg high 2.4 bg r down bg pull-down r ds(on) bg low 1.1 tg0,1 t r t f tg transition time: rise time fall time (note 5) c load = 3300pf c load = 3300pf 30 30 ns ns bg0,1 t r t f bg transition time: rise time fall time (note 5) c load = 3300pf c load = 3300pf 30 30 ns ns tg/bg t 1d top gate off to bottom gate on delay time c load = 3300pf each driver (note 5) 30 ns bg/tg t 2d bottom gate off to top gate on delay time c load = 3300pf each driver (note 5) 30 ns t on(min) minimum on-time (note 6) 90 ns intv cc regulator v intvcc internal v cc voltage no load 6v < v in < 38v 5.25 5.5 5.75 v v ldo int intv cc load regulation i cc = 0ma to 20ma 0.5 2 % v extvcc extv cc switchover voltage extv cc ramping positive (note 8) l 4.5 4.7 v v ldo ext extv cc voltage drop i cc = 20ma, v extvcc = 5v 50 100 mv v ldohys extv cc hysteresis 300 mv the l denotes the specifications which apply over the specified operating junction temperature range, otherwise specifications are at t a = 25c (note 2). v in = 12v, v run0,1 = 3.3v unless otherwise specified. 3874f ltc 3874
4 for more information www.linear.com/LTC3874 note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2: the LTC3874 is tested under pulsed load conditions such that t j t a . the LTC3874e is guaranteed to meet performance specifications from 0c to 85c. specifications over the C40c to 125c operating junction temperature range are assured by design, characterization and correlation with statistical process controls. the LTC3874i is guaranteed over the C40c to 125c operating junction temperature range. high junction temperatures degrade operating lifetimes; operating lifetime is derated for junction temperatures greater than 125c. note that the maximum ambient temperature consistent with these specifications is determined by specific operating conditions in conjunction with board layout, the rated package thermal impedance and other environmental factors. t j is calculated from the ambient temperature t a and power dissipation p d according to the following formula: t j = t a + (p d ? 43?c/w) note 3: output voltage is set and controlled by master controller in multiphase operations. note 4: dynamic supply current is higher due to the gate charge being delivered at the switching frequency. see application information. note 5: rise and fall times are measured using 10% and 90% levels. delay times are measured using 50% levels. note 6: the minimum on-time condition corresponds to an inductor peak-to-peak ripple current 40% of i max (see minimum on-time considerations in the applications information section). note 7: extv cc is enabled only if v in is higher than 7v. electrical characteristics the l denotes the specifications which apply over the specified operating junction temperature range, otherwise specifications are at t a = 25c (note 2). v in = 12v, v run0,1 = 3.3v unless otherwise specified. symbol parameter conditions min typ max units oscillator and phase-locked loop f range pll sync range l 250 1000 khz f nom nominal frequency v freq = 0.9v 500 khz i freq frequency setting current 9 10 11 a sync-0 sync to ch0 phase relationship based on the falling edge of sync and rising edge of tg0 phasmd = 0 phasmd = 1/3 ? intv cc phasmd = 2/3 ? intv cc phasmd = intv cc 180 60 120 90 deg deg deg deg sync-1 sync to ch1 phase relationship based on the falling edge of sync and rising edge of tg1 phasmd = 0 phasmd = 1/3 ? intv cc phasmd = 2/3 ? intv cc phasmd = intv cc 0 300 240 270 deg deg deg deg digital inputs run0, run1, mode0, mode1, fau lt0, fau lt1, lowdcr v ih input high threshold voltage l 2.0 v v il input low threshold voltage l 1.4 v 3874f ltc 3874
5 for more information www.linear.com/LTC3874 load current (a) 0.1 efficiency (%) 100 10 90 70 50 30 80 60 40 20 0 10 3874 g01 100 1 v in = 12v v out = 1.2v dcm ccm load current (a) 0.1 efficiency (%) 100 10 90 70 50 30 80 60 40 20 0 10 3874 g02 100 1 v in = 12v v out = 1.8v dcm ccm typical performance characteristics load step (discontinuous conduction mode) 3-phase with master controller ltc3866 inductor current at light load start-up into a pre-biased output with master controller ltc3875 dual phase efficiency and power loss vs output current load step (forced continuous mode) 3-phase with master controller ltc3866 efficiency vs output current and mode efficiency vs output current and mode v in = 12v v out = 1.2v i load 5a to 50a 50s/div 3874 g04 i l(master) 20a/div i l(slave1) 20a/div i l(slave0) 20a/div v out 200mv/div ac-coupled 50s/div 3874 g05 v in = 12v v out = 1.2v i load 5a to 50a i l(master) 20a/div i l(slave1) 20a/div i l(slave0) 20a/div v out 200mv/div ac-coupled v in = 12v v out = 1.2v i load = 2a 1s/div 3874 g06 forced continuous mode 5a/div discontinuous conduction mode 5a/div v in = 12v v out = 1.0v 20ms/div 3874 g06a run 5v/div ov v out 1v/div ov load current (a) 0 70 efficiency (%) power loss (w) 75 80 85 90 100 95 0 4 2 6 8 10 14 12 10 20 50 30 60 40 3874 g03 efficiency power loss 1.5m 0.32m 1.5m 0.32m v in = 12v v out = 1.8v ccm (t a = 25c unless otherwise specified) 3874f ltc 3874
6 for more information www.linear.com/LTC3874 typical performance characteristics quiescent current vs input voltage without extv cc v in (v) 5 5.5 5.3 5.1 4.3 4.1 3.5 3.7 3.9 4.5 4.7 4.9 25 35 3874 g14 10 15 20 40 30 supply current (ma) undervoltage lockout threshold (intv cc ) vs temperature temperature (c) ?50 4.1 3.9 2.9 3.7 2.7 3.1 3.5 2.5 3.3 95 3874 g12 ?5 45 125 uvlo threshold (v) falling rising intv cc line regulation current sense threshold vs i th voltage maximum current sense threshold vs common mode voltage (lowdcr = intv cc , v ith = 2.18v) v ith (v) 0 ?40 v isense (mv) ?20 0 20 40 60 100 80 0.5 1 2.5 1.5 3 2 3874 g09 lowdcr = l, range = h lowdcr = h, range = l lowdcr = h, range = h lowdcr = l, range = l v isense common mode voltage (v) 0 current sense threshold (mv) 10 15 3.5 5 0 1.00.5 2.0 2.5 3.0 1.5 20 25 30 3874 g10 i lim = gnd i lim = intv cc intv cc voltage (v) 6 4 5 2 3 1 0 v in (v) 0 105 15 30 35 3874 g08 40 20 25 quiescent current vs temperature without extv cc quiescent current (ma) 6 4 2 5 3 1 0 temperature (c) ?50 45 3874 g07 125 ?5 95 (t a = 25c unless otherwise specified) 3874f ltc 3874
7 for more information www.linear.com/LTC3874 pin functions mode0/mode1 (pin 1/pin 8): dcm/ccm mode control pins. each channel runs in forced continuous mode if the mode pin is logic high. there is an internal 500 k pull-down resistor on mode pin. to select discontinuous conduction mode, float or pull down the mode pin. i sense0 + /i sense1 + (pin 2/pin 7): current sense compara- tor inputs . the (+) inputs to the current comparators are normally connected to dcr sensing networks. i sense0 ? /i sense1 ? (pin3/pin6): current sense compara- tor inputs . the (?) inputs to the current comparators are connected to the outputs. run0/run 1 ( pin 4/pin 5): enable run inputs. logic high on run pin enables the corresponding channel. i th0 /i th1 ( pin 28/pin 9): current control threshold. each associated channel s current comparator tripping threshold increases with its i th voltage. these pins must be con- nected to the master controllers i th pins. freq (pin 10): frequency set pin. there is a precision 10a current flowing out of this pin. a resistor to ground sets a voltage which in turn programs the frequency. this pin sets the default switching frequency when there is no external clock on the sync pin. see the application section for detailed information. ilim ( pin 11): current comparators sense voltage limit. program a dc voltage at this pin to set the maximum cur - rent sense threshold for the current comparators. sync ( pin 12): external clock synchronization input. if an external clock is present at this pin, the switching frequency will be synchronized to the falling edge of external clock. tie this pin to gnd if not used. phasmd (pin 13): phase set pin. this pin determines the relative phases between the external clock on pin sync and the internal controllers. see table 1 in the operation section for details. tg0/tg1 (pin 24/pin 14): top gate driver outputs. these are the outputs of floating drivers with a voltage swing equal to intv cc superimposed on the switch node voltages. sw0/sw1 (pin 23/pin 15): switch node connections. connect these pins to the output filter inductor, bottom n-channel mosfet drain and top n-channel mosfet source. voltage swing at the pins are from a schottky diode (external) voltage drop below ground to v in . boost0/boost1 (pin 22/pin 16): boosted floating driver supplies. the (+) terminal of the bootstrap capacitors con - nect to these pins. these pins swing from a diode voltage drop below int v cc up to v in + intv cc . bg0/bg1 (pin 21/pin 17): bottom gate driver outputs. these pins drive the gates of the bottom n-channel mos - fets between gnd and intv cc . extv cc ( pin 18): external power input to an internal switch connected to intv cc . the switch closes and supplies the ic power, bypassing the internal low dropout regulator, whenever extv cc is higher than 4.7 v and v in is greater than 7v. do not exceed 6v on this pin. intv cc (pin 19): internal 5.5 v regulator output. the con- trol cir cuits are powered from this voltage. decouple this pin to gnd with a minimum of 4.7 f low esr tantalum or ceramic capacitor. v in (pin 20): main input supply. decouple this pin to gnd with a capacitor (0.1f to 1f). fau lt0, fau lt1 (pin 26/pin 25): master controller fault inputs. connect these pins to the master chip fault indica - tor pins to respond to the fault signals from the master controller. when a fault pin is floating or low, both tg and bg pins are pulled down in the corresponding chan - nel. there is an internal 500 k pull-down resistor on each f ault pin. lowdcr (pin 27): sub-milliohm dcr current sensing enable pin. there is an internal 500 k pull-up resistor be- tween lowdcr pin and intv cc . floating or pulling this pin logic high will enable the sub-milliohm dcr current sensing. puling this pin logic low will disable the sub- milliohm dcr current sensing. gnd ( exposed pad pin 29): ground. connect this pad, through vias, to a solid ground plane under the circuit . the sources of the bottom n-channel mosfets, the (C) terminal of c intvcc , and the (C) terminal of c in should connect to this ground plane as closely as possible to the ic. all small-signal components and compensation components should also connect to this ground plane. 3874f ltc 3874
8 for more information www.linear.com/LTC3874 functional block diagram 10a extv cc intv cc intv cc i rev i cmp intv cc i th0 i lim i sense0 + i sense0 ? c b d b c vcc boost0 m1 on 5k rev uvlo fcnt run faultb m2 1.7v run0 mode0 fault0 tg0 sw0 bg0 gnd v in v in v out0 c out0 c in 4.7v freq sync phasmd sync/phase detect osc pll-sync uvlo dc amp slope compensation i lim range select hi: 1:1 lo: 1:1.8 switch logic and anti- shoot- through s r q 5.5v reg + + ref ? + ? + ? + + ? + ? lowdcr + ? + ? 3874 bd 1 60k 1 5k one of two channels (ch0) shown 3874f ltc 3874
9 for more information www.linear.com/LTC3874 operation main control loop the LTC3874 is a constant frequency, lt c proprietary cur- rent mode step - down slave controller for parallel operation with master controllers. during normal operation, each top mosfet is turned on when the clock for that channel sets the rs latch, and turned off when the main current comparator, i cmp , resets the rs latch. the peak inductor current at which i cmp resets the rs latch is controlled by the voltage on the i th pin, which is the output of the master controller. when the load current increases, the master controller increases the i th voltage, which in turn causes the peak current in the corresponding slave channels to increase, until the average inductor current matches the new load current. after the top mosfet has turned off, the bottom mosfet is turned on until the beginning of the next cycle in continuous conduction mode ( ccm) or until the inductor current starts to reverse, as indicated by the reverse current comparator i rev , in discontinuous conduction mode ( dcm). LTC3874 slave controllers do not regulate the output voltage but regulate the current in each channel for current sharing with the master con - trollers. output voltage regulation is achieved through the voltage feedback control loop in the master controllers. sub-milliohm dcr current sensing the LTC3874 employs a unique architecture to enhance the signal-to-noise ratio that enables it to operate with a small sense signal of a sub-milliohm value inductor dcr to improve power efficiency and reduce jitter due to switching noise. floating or pulling the lowdcr pin high will enable sub- milliohm dcr current sensing. the LTC3874 can sense a dcr value as low as 0.2 m with careful pcb layout. the proprietary signal processing circuit provides a 14db signal-to-noise ratio improvement. as with conventional current mode architectures, the current limit threshold is still a function of the inductor peak current and the dcr value, and can be accurately set with the ilim and i th pins. intv cc /extv cc power power for the top and bottom mosfet drivers and most other internal circuitry is derived from the intv cc pin. when the extv cc pin is left open or tied to a voltage less than 4.7v , an internal 5.5 v linear regulator supplies intv cc power from v in . if extv cc is taken above 4.7 v and v in is higher than 7 v, the 5.5 v regulator is turned off and an internal switch is turned on connecting extv cc . extv cc can be applied before v in . using the extv cc allows the intv cc power to be drawn from an external source. each top mosfet driver is biased from the floating boot- strap capacitor c b , which normally recharges during each off cycle through an external diode when the top mosfet turns off. if the input voltage v in decreases to a voltage close to v out , the loop may enter dropout and attempt to turn on the top mosfet continuously. a dropout detector detects this and forces the top mosfet off for about one- twelfth of the clock period plus 100 ns every three cycles to allow c b to recharge. start-up and shutdown (run0, run1) the two channels of the LTC3874 can be independently shut down using the run0 and run1 pins. pulling either of these pins below 1.4 v shuts down the main control circuits for that channel. during shutdown, both tg and bg are pulled down to turn off the external power mosfets. pulling either of these pins above 2 v enables the controller. the run0/1 pins are actively pulled down until the intv cc voltage passes the undervoltage lockout threshold of 3.8 v. for multiphase operation, the run0/1 pins must be connected together and driven by the run pins on the master controller. because a large rc filter in the LTC3874 needs to settle during initialization, the run pins can only be pulled up 4 ms after v in is ready. do not exceed the absolute maximum rating of 6 v on these pins. 3874f ltc 3874
10 for more information www.linear.com/LTC3874 operation the start-up of each channels output voltage v out is controlled by the master controller. after the run pins are released, the master controller drives the output based on the programmed delay time and rise time. the slave controller LTC3874 follows the i th voltage set by the master to supply the same current to the output during startup. light load current operation (discontinuous conduction mode, continuous conduction mode) the LTC3874 can operate either in discontinuous conduc - tion mode or forced continuous conduction mode. to select forced continuous mode, tie the mode pin to a dc voltage above 2v ( e.g., intv cc ). to select discontinuous conduction mode, tie the mode pin to a dc voltage below 1.4v ( e.g., gnd).in forced continuous mode, the induc - tor current is allowed to reverse at light loads or under large transient conditions. the peak inductor current is determined by the voltage on the i th pin. in this mode, the efficiency at light loads is lower than in discontinuous mode. however, continuous mode has the advantages of lower output ripple and less interference with audio circuitry. when the mode pin is connected to gnd, the LTC3874 operates in discontinuous mode at light loads. at very light loads, the current comparator i cmp may remain tripped for several cycles and force the external top mosfet to stay off for the same number of cycles ( i.e., skipping pulses). this mode provides higher light load efficiency than forced continuous mode and the inductor current is not allowed to reverse. there is a 500 k pull-down resistor internally connected to the mode pin. if the mode0/1 pins are left floating, both channels are in discontinuous conduction mode by default. multichip operations (phasmd and sync pins) the phasmd pin determines the relative phases between the internal channels as well as the external clock signal on sync pin as shown in table 1. the phases tabulated are relative to zero degree phase being defined as the falling edge of the clock on sync pin. table 1 phasmd channel 0 phase channel 1 phase gnd 180 0 1/3 intv cc 60 300 2/3 intv cc or float 120 240 intv cc 90 270 the sync pin is used to synchronize switching frequency between the master and slave controllers. input capacitance esr requirements and efficiency losses are substantially reduced because the peak current drawn from the input capacitor is effectively divided by the number of phases used and power loss is proportional to the rms current squared. a two stage, single output voltage implementa - tion can reduce input path power loss by 75% and radi- cally reduce the required rms current rating of the input capacitor(s). single output multiphase operation the LTC3874 is configured for single output multiphase converters with a master controller by making these connections ? tie all the i th pins of paralleled channels together for current sharing between masters and slaves; ? tie all sync or pllin pins of paralleled channels to- gether or tie the master chips clkout pin to the slave chip s sync pin for switching frequency synchronization among channels. ? tie all the run pins of paralleled channels together for startup and shutdown at the same time. ? tie the fault indictor pin of the master controller if avail- able to the fault pin of the slave controller for fault protection. ? the LTC3874 mode pin can be tied to the master chip pgood pin for start-up control. during soft-start, the LTC3874 operates in dcm mode. when the soft-start interval is done, the LTC3874 operates in ccm mode. examples of single output multiphase converters are shown in figure 1. 3874f ltc 3874
11 for more information www.linear.com/LTC3874 figure 1. multiphase operation frequency selection and phase-locked loop (freq and sync pins) the selection of switching frequency is a trade- off between efficiency and component size. low frequency operation increases efficiency by reducing mosfet switching losses, but requires larger inductance and/or capacitance to main - tain low output ripple voltage. the switching frequency of the LTC3874 controllers can be selected using the freq pin. if the sync pin is not being driven by an external clock source, the freq pin can be used to program the control - lers operating frequency from 250 khz to 1 mhz. there is a precision 10 a current flowing out of the freq pin, so the user can program the controller s switching frequency with a single resistor to gnd. a curve is provided later in the application section showing the relationship between the voltage on the freq pin and switching frequency ( figure 5). a phase-locked loop ( pll) is integrated in the LTC3874 to synchronize the internal oscillator to an external clock source on the sync pin. the pll loop filter network is integrated inside the LTC3874. the phase-locked loop is capable of locking to any frequency within the range of 250 khz to 1 mhz. the frequency setting resistor should always be present to set the controllers initial switching frequency before locking to the external clock. LTC3874 240 120 ltc3866 0 3 phase operation 6 phase operation 4 phase operation ch0 ch1 LTC3874 90 270 phasmd = gnd phasmd = float ch1 ch2 ch0 ch1 LTC3874 120 300 ltc3875 0 240 phasmd = gnd phasmd = intv cc phasmd = 2/3 intv cc ch1 ch2 ch0 ch1 LTC3874 sync clkout clkout sync sync clkout sync 60 180 ch0 ch1 3874 f01 phasmd = 1/3 intv cc ltc3875 0 180 operation 3874f ltc 3874
12 for more information www.linear.com/LTC3874 applications information the typical application on the first page of this data sheet is a basic LTC3874 application circuit configured as a slave controller. in paralleled operation, the current sensing scheme and circuit parameters in the LTC3874 have to be the same as the master controller to achieve balanced current sharing between masters and slaves. input and output capacitors are selected based on rms current rating, ripple and transient specs. current limit programming to match the master controller current limit, each chan - nel of the LTC3874 can be programmed separately with the ilim and lowdcr pins. the 4- level logic input pin ilim setup summary is shown in table 2. when ilim is grounded, both channels are set to be low current range. when ilim is tied to intv cc , both channels are set to be high current range. which setting should be used? for balanced load cur - rent sharing, use the same current range setting as in the master controller. note, the LTC3874 does not have active clamping circuit on i th pin for peak current limit and over current protection. over current protection relies on the master controller to drive the i th pin not to exceed the clamped voltage. the relationship between the current sense threshold and i th voltage can be found in table 3. table 2. ilim vs range ilim channel 0 current limit channel 1 current limit gnd range low range low 1/3 int v cc range high range low 2/3 intv cc or float range low range high intvcc range high range high table 3. current sense threshold vs i th voltage i th (v) current sense threshold (mv) lowdcr = h lowdcr = l range = h range = l range = h range = l 2.40 32.5 18.1 81.3 45.1 2.33 31.4 17.4 78.4 43.6 2.26 30.2 16.8 75.6 42.0 2.20 29.1 16.2 72.7 40.4 2.18 28.8 16.0 72.0 40.0 2.13 28.0 15.5 69.9 38.8 2.06 26.8 14.9 67.1 37.3 1.99 25.7 14.3 64.2 35.7 1.92 24.6 13.6 61.4 34.1 1.85 23.4 13.0 58.5 32.5 1.79 22.3 12.4 55.7 30.9 1.72 21.1 11.7 52.8 29.4 1.68 20.4 11.3 51.0 28.4 1.58 18.9 10.5 47.2 26.2 1.51 17.7 9.9 44.3 24.6 1.45 16.6 9.2 41.5 23.0 1.38 15.5 8.6 38.6 21.4 i sense + and i sense ? pins i sense + and i sense C are the inputs to the current com- parators. when the lowdcr pin is high, their common mode input voltage range is 0 v to 3.5 v. i sense C should be connected directly to v out of the master controller. i sense + is connected to an r ? c filter with time constant one-fifth of l/dcr of the output inductor. care must be taken not to float these pins during normal operation. filter components, especially capacitors, must be placed close to the LTC3874, and the sense lines should run close 3874f ltc 3874
13 for more information www.linear.com/LTC3874 applications information together to a kelvin connection underneath the current sense element. the LTC3874 is designed to be used with a sub-milliohm dcr value; without proper care, parasitic resistance, capacitance and inductance will degrade the current sense signal integrity, making the programmed current limit unpredictable. in figure?2, resistor r must be placed close to the output inductor and capacitor c close to the ic pins to prevent noise coupling to the sense signal. the LTC3874 can also be used like any conventional cur - rent mode controller by disabling the lowdcr pin, con- necting it to ground. an rc filter can be used to sense the output inductor signal and connects to the i sense + pin. its time constant, r ? c, should equal to l/dcr of the output inductor. by pulling down the lowdcr pin, the current limit increases by 2.5 times. see table 3 for details. in these applications, the common mode operating voltage range of i sense + , i sense C is from 0v to 5.5v. table 4. output voltage range vs lowdcr pin lowdcr output voltage low 0v to 5.5v high 0v to 3.5v than 1 m for high current inductors. in high current and low output voltage applications, conduction loss of a high dcr or a sense resistor will cause a significant reduction in power efficiency. for a specific output requirement, choose the inductor with the dcr that satisfies the maxi - mum desirable sense voltage, and use the relationship of the sense pin filters to output inductor characteristics as depicted below. dcr = v isense(max) i max + i l 2 rc = l/(5 ? dcr) when the lowdcr pin is high rc = l/dcr when the lowdcr pin is low where: v isense(max) : maximum sense voltage for a given i th voltage i max : maximum load current i l : inductor ripple current l, dcr: output inductor characteristics r, c: filter time constant to ensure that the load current will be delivered over the full operating temperature range, the temperature coefficient of the dcr resistance, approximately 0.4%/ c, should be taken into consideration. typically, c is selected in the range of 0.047 f to 0.47f. this forces r to around 2 k, reducing error that might have been caused by the i sense pins 1ua current. there will be some power loss in r that relates to the duty cycle. it will be highest in continuous mode at maximum input voltage: p loss (r) = v in(max) ? v out ( ) v out r ensure that r has a power rating higher than this value. however, dcr sensing eliminates the conduction loss of a sense resistor; it will provide a better efficiency at heavy loads. to maintain a good signal-to-noise ratio for the current sense signal, using a minimum v isense of figure 2 inductor dcr current sensing v in v in intv cc boost tg sw bg gnd i sense + i sense ? LTC3874 v out 3874 f02 inductance dcrl c r inductor dcr current sensing the LTC3874 is specifically designed for high load current applications requiring the highest possible efficiency; it is capable of sensing the signal of an inductor dcr in the sub-milliohm range (figure 2). the dcr is the dc winding resistance of the inductors copper, which is often less 3874f ltc 3874
14 for more information www.linear.com/LTC3874 applications information 2mv for duty cycles less than 40% is desirable when the lowdcr pin is high; use a minimum v isense of 10mv for duty cycles less than 40% when the lowdcr pin is low. the actual ripple voltage will be determined by the following equation: v isense = v out v in v in ? v out r c f osc ? ? ? ? ? ? inductor value calculation given the desired input and output voltages, the inductor value and operating frequency, f osc , directly determine the inductors peak-to-peak ripple current: i ripple = v out v in v in ? v out f osc l ? ? ? ? ? ? lower ripple current reduces core losses in the inductor, esr losses in the output capacitors, and output voltage ripple. thus, highest efficiency operation is obtained at low frequency with a small ripple current. achieving this, however, requires a large inductor. a reasonable starting point is to choose a ripple current that is about 40% of i out(max) . note that the largest ripple current occurs at the highest input voltage. to guarantee that ripple current does not exceed a specified maximum, the inductor should be chosen according to: l v in ? v out f osc i ripple v out v in inductor core selection once the inductance value is determined, the type of in- ductor must be selected. core loss is independent of core size for a fixed inductor value, but it is very dependent on inductance selected. as inductance increases, core losses go down. unfortunately, increased inductance requires more turns of wire and therefore copper losses will increase. ferrite designs have very low core loss and are preferred at high switching frequencies, so design goals can concentrate on copper loss and preventing saturation. ferrite core material saturates hard, which means that inductance collapses abruptly when the peak design current is exceeded. this results in an abrupt increase in inductor ripple current and consequent output voltage ripple. do not allow the core to saturate! power mosfet and schottky diode (optional) selection at least two external power mosfets need to be selected: one n-channel mosfet for the top ( main) switch and one or more n - channel mosfet(s) for the bottom (synchro - nous) switch . the number, type and on-resistance of all mosfets selected take into account the voltage step - down ratio as well as the actual position ( main or synchronous) in which the mosfet will be used. a much smaller and much lower input capacitance mosfet should be used for the top mosfet in applications that have an output voltage that is less than one-third of the input voltage. in applications where v in >> v out , the top mosfets on- resistance is normally less important for overall efficiency than its input capacitance at operating frequencies above 300khz. mosfet manufacturers have designed special purpose devices that provide reasonably low on- resistance with significantly reduced input capacitance for the main switch application in switching regulators. the peak-to-peak mosfet gate drive levels are set by the internal regulator voltage, v intvcc , requiring the use of logic-level threshold mosfets in most applications. pay close attention to the bv dss specification for the mosfets as well; many of the logic-level mosfets are limited to 30v or less. selection criteria for the power mosfets include the on-resistance, r ds(on) , input capacitance, input voltage and maximum output current. mosfet input capacitance is a combination of several components but can be taken from the typical gate charge cur ve included on most data sheets ( figure 3). the curve is generated by forcing a constant input current into the gate of a common source, current source loaded stage and then plotting the gate voltage versus time. 3874f ltc 3874
15 for more information www.linear.com/LTC3874 the initial slope is the effect of the gate-to-source and the gate-to-drain capacitance. the flat portion of the curve is the result of the miller multiplication effect of the drain-to-gate capacitance as the drain drops the voltage across the current source load. the upper sloping line is due to the drain-to-gate accumulation capacitance and the gate-to-source capacitance. the miller charge (the increase in coulombs on the horizontal axis from a to b while the curve is flat) is specified for a given v ds drain voltage, but can be adjusted for different v ds voltages by multiplying the ratio of the application v ds to the curve specified v ds values. a way to estimate the c miller term is to take the change in gate charge from points a and b on a manufacturers data sheet and divide by the stated v ds voltage specified. c miller is the most important se- lection criteria for determining the transition loss term in the top mosfet but is not directly specified on mosfet data sheets. c rss and c os are specified sometimes but definitions of these parameters are not included. when the controller is operating in continuous mode the duty cycles for the top and bottom mosfet s are given by: main switch duty cycle = v out v in synchronous switch duty cycle = v in ? v out v in ? ? ? ? ? ? applications information the power dissipation for the main and synchronous mosfets at maximum output current are given by: p main = v out v in i max ( ) 2 1 + ( ) r ds(on) + v in ( ) 2 i max 2 ? ? ? ? ? ? r dr ( ) c miller ( ) 1 v intvcc ? v th(min) + 1 v th(min) ? ? ? ? ? ? ? ? f p sync = v in ? v out v in i max ( ) 2 1 + ( ) r ds(on) where i is the temperature dependency of r ds(on) , r dr is the effective top driver resistance (approximately 2 at v gs = v miller ), v in is the drain potential and the change in drain potential in the particular application. v th(min) is the data sheet specified typical gate threshold voltage specified in the power mosfet data sheet at the specified drain current. c miller is the calculated capacitance using the gate charge curve from the mosfet data sheet and the technique described above. both mosfets have i 2 r losses while the topside n- channel equation includes an additional term for transition losses, which peak at the highest input voltage. for v in < 20v, the high current efficiency generally improves with larger mosfets, while for v in > 20 v, the transition losses rapidly increase to the point that the use of a higher r ds(on) device with lower c miller actually provides higher efficiency. the synchronous mosfet losses are greatest at high input voltage when the top switch duty factor is low or during a short-circuit when the synchronous switch is on close to 100% of the period. the term (1 + i ) is generally given for a mosfet in the form of a normalized r ds(on) vs temperature curve, but i = 0.005/ c can be used as an approximation for low voltage mosfets. + ? v ds v in 3874 f03 v gs miller effect q in a b c miller = (q b ? q a )/v ds v gs v + ? figure 3. gate charge characteristic 3874f ltc 3874
16 for more information www.linear.com/LTC3874 applications information an optional schottky diode across the synchronous mosfet conducts during the dead time between the con- duction of the two large power mosfets. this prevents the body diode of the bottom mosfet from turning on, storing charge during the dead time and requiring a reverse- recov - ery period which could cost as much as several percent in e fficiency. a 2a to 8 a schottky is generally a good com - promise for both regions of operation due to the relatively small average current. larger diodes result in additional transition loss due to their larger junction capacitance. intv cc regulators and extv cc the LTC3874 features a pmos ldo that supplies power to intv cc from the v in supply. intv cc powers the gate drivers and most of the LTC3874s internal circuitry. the linear regulator regulates the voltage at the intv cc pin to 5.5 v when v in is greater than 6 v. extv cc connects to intv cc through another p-channel mosfet and can supply the needed power when its voltage is higher than 4.7v and v in is higher than 7 v. each of these can supply a peak current of 100 ma and must be bypassed to ground with a minimum value of 4.7f ceramic capacitor or low esr electrolytic capacitor. no matter what type of bulk capacitor is used, an additional 0.1 f ceramic capacitor placed directly adjacent to the intv cc and gnd pins is highly recommended. good bypassing is needed to supply the high transient currents required by the mosfet gate drivers and to prevent interaction between the channels. high input voltage applications in which large mosfets are being driven at high frequencies may cause the maxi - mum junction temperature rating for the LTC3874 to be exceeded. the intv cc current, which is dominated by the gate charge current, may be supplied by either the 5.5v linear regulator from v in or extv cc . when the voltage on the extv cc pin is less than 4.4 v, the linear regulator is enabled. power dissipation for the ic in this case is high- est and is equal to v in ? i intvcc . the gate charge current is dependent on operating frequency. the junction tem- perature can be estimated by using the equations given in note 2 of the electrical characteristics. for example, the LTC3874 intv cc current is limited to less than 34ma from a 38 v supply in the ufd package and not using the extv cc supply: t j = 70c + (34ma)(38v)(43c/w) = 125c to prevent the maximum junction temperature from being exceeded, the input supply current must be checked while operating in continuous conduction mode ( mode = intv cc ) at maximum v in . when the voltage applied to extv cc rises above 4.7 v and v in above 7 v, the intv cc linear regula- tor is turned off and the extv cc is connected to intv cc . using the extv cc allows the mosfet driver and control power to be derived from other high efficiency sources such as +5 v rails in the system. do not apply more than 6v to the extv cc pin. significant efficiency and thermal gains can be realized by powering intv cc from extv cc . tying the extv cc pin to a 5 v supply reduces the junction temperature in the previous example from 125c to: t j = 70c + (34ma)(5v)(43c/w) = 77c however, for low voltage outputs, additional circuitry is required to derive intv cc power from the output. the following list summarizes the three possible connec- tions for extv cc : 1. extv cc left open ( or grounded). this will cause intv cc to be powered from the internal ldo resulting in an efficiency penalty of up to 10% at high input voltages. 2. extv cc connected to an external supply. if a 5 v external supply is available, it may be used to power extv cc providing it is compatible with the mosfet gate drive requirements. 3. extv cc connected to an output-derived boost network. for 3.3 v and other low voltage regulators, efficiency gains can still be realized by connecting extv cc to an output-derived voltage that has been boosted to greater than 4.7v. 3874f ltc 3874
17 for more information www.linear.com/LTC3874 applications information for applications where the main input power is 5 v, tie the v in and intv cc pins together and tie the combined pins to the 5 v input with a 1 or 2.2 resistor as shown in figure 4 to minimize the voltage drop caused by the gate charge current. this will override the intv cc linear regulator and will prevent intv cc from dropping too low due to the dropout voltage. make sure the intv cc voltage is at or exceeds the r ds(on) test voltage for the mosfet, which is typically 4.5v for logic-level devices. topside mosfet driver supply (c b , d b ) external bootstrap capacitor, c b , connected to the boost pin, supplies the gate drive voltages for the topside mosfet. capacitor c b in the functional diagram is charged though external diode d b from intv cc when the sw pin is low. when the topside mosfet is to be turned on, the driver places the c b voltage across the gate source of the mosfet. this enhances the mosfet and turns on the topside switch. the switch node voltage, sw, rises to v in and the boost pin follows. with the topside mosfet on, the boost voltage is above the input supply: v boost = v in + v intvcc C v db the value of the boost capacitor, c b , needs to be 100 times that of the total input capacitance of the topside mosfet (s ). the reverse breakdown of the external schottky diode must be greater than v in(max) . when adjusting the gate drive level, the final arbiter is the total input current for the regulator. if a change is made and the input current decreases, then the efficiency has improved. if there is no change in input current, then there is no change in efficiency. r vin 1 c in 3874 f04 5v c intvcc 4.7f + intv cc LTC3874 v in figure 4. setup for a 5v input undervoltage lockout the LTC3874 has a precision uvlo comparator constantly monitoring the intv cc voltage to ensure that an adequate gate-drive voltage is present. it locks out the switching action and pulls down run pins when intv cc is below 3.5v. in multiphase operation, when the LTC3874 is in undervoltage lockout, the run pin is pulled down to dis - able the masters switching action. to prevent oscillation when there is a disturbance on the intv cc , the uvlo comparator has 300mv of precision hysteresis. phase-locked loop and frequency synchronization the LTC3874 has a phase-locked loop ( pll) comprised of an internal voltage-controlled oscillator ( vco) and a phase detector. this allows the internal clock to be locked to the falling edge of an external clock signal applied to the sync pin. the turn-on of the top mosfet is synchronized or out-of-phase with the falling edge of external clock. the phase detector is an edge sensitive digital type that provides zero degrees phase shift between the external and internal oscillators. this type of phase detector does not exhibit false lock to harmonics of the external clock. the output of the phase detector is a pair of complemen- tary current sources that charge or discharge the internal filter network. there is a precision 10 a of current flowing out of the freq pin. this allows the user to use a single resistor to gnd to set the switching frequency when no external clock is applied to the sync pin. the internal switch between the freq pin and the integrated pll filter network is on, allowing the filter network to be pre- charged to the same voltage potential as the freq pin. the relationship between the voltage on the freq pin and the operating frequency is shown in figure 5 and specified in the electrical characteristic table. if an external clock is detected on the sync pin, the internal switch mentioned above will turn off and isolate the influence of the freq pin. note that the LTC3874 can only be synchronized to an external clock whose frequency is within the range of the LTC3874s internal vco. this is guaranteed to be between 250 khz and 1 mhz. a simplified block diagram is shown in figure 6. 3874f ltc 3874
18 for more information www.linear.com/LTC3874 applications information if the external clock frequency is greater than the inter- nal oscillator s frequency, f osc , then current is sourced continuously from the phase detector output, pulling up the filter network. when the external clock frequency is less than f osc , current is sunk continuously, pulling down the filter network. if the external and internal frequencies are the same but exhibit a phase difference, the current sources turn on for an amount of time corresponding to the phase difference. the voltage on the filter network is adjusted until the phase and frequency of the internal and external oscillators are identical. at the stable operating point, the phase detector output is high impedance and the filter capacitor holds the voltage. typically, the external clock ( on the sync pin) input high threshold is 2v, while the input low threshold is 1.4v. fault protection and response master controllers monitor system voltage, current, tem - perature and provide many protection features during all kinds of fault conditions. the LTC3874 slave controllers do not provide as many fault protections as master con - trollers but respond to the fault signal from the master controller. fa u lt0 and fau lt1 pins are designed to share the fault signal between masters and slaves. in a typical parallel application, connect the fault pins on LTC3874 to the master fault indictor pins, so that the slave controller can respond to all fault signals from the master. when the fault pin is pulled below 1.4 v, both tg and bg in the corresponding channel are pulled down and external mosfets are turned off. when the fault pin voltage is above 2 v, the corresponding channel is back to normal operation. during fault conditions, all internal circuits in the LTC3874 are still running so the slave controllers can immediately return to normal operation when the fault pin is released. the LTC3874 has internal thermal shutdown protection which pulls all tg and bg pins low when the junction temperature is higher than 160 c. in thermal shutdown, the fau lt0 and fau lt1 pins are also pulled low. the run pins are not internally pulled low. there is a 500 k pull- down resistor on each fault pin which sets the default voltage on the fault pins low if the fault pins are floating. transient response and loop stability in a typical parallel operation, the LTC3874 cooperates with master controllers to supply more current. to achieve balanced current sharing between master and slave, it is recommended that each slave channel copies the power stage design from the master channel. select the same inductors, same power mosfets, and same output capaci - tors between the master and slave channels. control loop and compensation design on the i th pin should start with the single phase operation of the master controller. the multiphase transient response and loop stability is almost the same as the single phase operation of the master by tying the i th pins together between master and slaves. for example, design the compensation for a single phase 1.8v/20a output using ltc3866 with a 0.33 h inductor and 530 f output capacitors. to extend the output to digital phase/ frequency detector sync vco 2.4v 5.5v 10a r set 3874 f06 freq external oscillator sync figure 6. phase-locked loop block diagram figure 5. relationship between oscillator frequency and voltage at the freq pin freq pin voltage (v) 0 frequency (khz) 0.5 1 1.5 2 3874 f05 2.5 0 600 400 1600 1200 1400 200 1000 800 3874f ltc 3874
19 for more information www.linear.com/LTC3874 applications information 1.8v/40a, simply parallel one channel of LTC3874 with the same inductor and output capacitors ( total output capacitors are 1060 f) and tie the i th pin of LTC3874 to the master i th . the loop stability and transient responses of the two phase converter are very similar to the single phase design without any extra compensator on the i th pin of the slave controller. furthermore, ltpowercad is provided on the lt c website as a free download for transient and stability analysis. to minimize the high frequency noise on the i th trace between master and slave i th pins, a small filter capacitor in the range of tens of pf can be placed closely at each i th pin of the slave controller. this small capacitor normally does not significantly affect the closed-loop bandwidth but increases the gain margin at high frequency. mode selection and pre-biased startup there may be situations that require the power supply to start up with a pre-bias on the output capacitors. in this case, it is desirable to start up without discharging the output capacitors. the LTC3874 can be configured to operate in dcm mode for pre-biased start-up. the master chips pgood pin can be connected to the mode pins of the LTC3874 to ensure the dcm operation at startup and ccm operation in steady state. minimum on-time considerations minimum on-time t on(min) is the smallest time duration that the LTC3874 is capable of turning on the top mosfet. it is determined by internal timing delays and the gate charge required to turn on the top mosfet. low duty cycle applications may approach this minimum on-time limit and care should be taken to ensure that: t on(min) < v out v in f if the duty cycle falls below what can be accommodated by the minimum on-time, the controller will begin to skip cycles. the output voltage will continue to be regulated, but the ripple voltage and current will increase. the minimum on-time for the LTC3874 is approximately 90 ns, with rea - sonably good pcb layout, minimum 30% inductor current ripple and at least 2mv C 3mv (10mv C 15 mv when the lowdcr pin is low) ripple on the current sense signal. the minimum on-time can be affected by pcb switch - ing noise in the current loop. as the peak sense voltage decreases the minimum on-time gradually increases to 130ns. this is of particular concern in forced continuous applications with low ripple current at light loads. if the duty cycle drops below the minimum on-time limit in this situation, a significant amount of cycle skipping can occur with correspondingly larger current and voltage ripple. pc board layout checklist when laying out the printed circuit board, the following checklist should be used to ensure proper operation of the ic. these items are also illustrated graphically in the layout diagram of figure 7. figure 8 illustrates the current waveforms present in the various branches of the 2-phase synchronous regulators operating in the continuous mode. check the following in the pc layout: 1. are the top n-channel mosfets m1 and m3 located within 1 cm of each other with a common drain connec - tion at c in ? do not attempt to split the input decoupling for the two channels as it can cause a large resonant loop. 2. are the signal and power grounds kept separate? the combined ic signal ground pin and the ground return of c intvcc must return to the combined c out (C) terminals. the i th traces should be as short as possible. the path formed by the top n-channel mosfet, schottky diode and the c in capacitor should have short leads and pc trace lengths. the output capacitor (C) terminals should be connected as close as possible to the (C) terminals of the input capacitor by placing the capacitors next to each other and away from the schottky loop described above. 3874f ltc 3874
20 for more information www.linear.com/LTC3874 3. are the i sense + and i sense C leads routed together with minimum pc trace spacing? the filter capacitor between i sense + and i sense C should be as close as possible to the ic. ensure accurate current sensing with kelvin connections at the sense resistor or inductor, whichever is used for current sensing. 4. is the intv cc decoupling capacitor connected close to the ic, between the intv cc and the power ground pins? this capacitor carries the mosfet drivers cur- rent peaks . an additional 1 f ceramic capacitor placed immediately next to the intv cc and gnd pins can help improve noise performance substantially. 5. keep the switching nodes ( sw1, sw0), top gate nodes (tg1, tg0), and boost nodes ( boost1, boost0) away from sensitive small-signal nodes, especially from the opposite channels current sensing feedback pins. all of these nodes have very large and fast moving signals and therefore should be kept on the output side of the LTC3874 and occupy minimum pc trace area. if dcr sensing is used, place the resistor (figure 2, r) close to the switching node. 6. use a modified star ground technique: a low impedance, large copper area central grounding point on the same side of the pc board as the input and output capacitors with tie-ins for the bottom of the intv cc decoupling capacitor, the bottom of the voltage feedback resistive divider and the gnd pin of the ic. pc board layout debugging start with one controller at a time. it is helpful to use a dc-50mhz current probe to monitor the current in the inductor while testing the circuit. monitor the output switching node ( sw pin) to synchronize the oscilloscope to the internal oscillator and probe the actual output voltage as well. check for proper performance over the operating voltage and current range expected in the application. the frequency of operation should be maintained over the input applications information voltage range down to dropout and until the output load drops below the low current operation threshold. the duty cycle percentage should be maintained from cycle to cycle in a well- designed, low noise pcb implementation. variation in the duty cycle at a subharmonic rate can sug - gest noise pickup at the current or voltage sensing inputs or inadequate loop compensation. overcompensation of the loop can be used to tame a poor pc layout if regulator bandwidth optimization is not required. only after each controller is checked for its individual performance should both controllers be turned on at the same time. a particularly difficult region of operation is when one controller channel is nearing its current comparator trip point when the other channel is turning on its top mosfet. this occurs around 50% duty cycle on either channel due to the phasing of the internal clocks and may cause minor duty cycle jitter. reduce v in from its nominal level to verify operation of the regulator in dropout. check the operation of the un- dervoltage lockout circuit by further lowering v in while monitoring the outputs to verify operation. investigate whether any problems exist only at higher out - put currents or only at higher input voltages. if problems coincide with high input voltages and low output currents, look for capacitive coupling between the boost, sw, tg, and possibly bg connections and the sensitive voltage and current pins. the capacitor placed across the current sensing pins needs to be placed immediately adjacent to the pins of the ic. this capacitor helps to minimize the effects of differential noise injection due to high frequency capacitive coupling. if problems are encountered with high current output loading at lower input voltages, look for inductive coupling between c in , schottky and the top mosfet components to the sensitive current and voltage sensing traces. in addition, investigate common ground path voltage pickup between these components and the gnd pin of the ic. 3874f ltc 3874
21 for more information www.linear.com/LTC3874 figure 7. recommended printed circuit layout diagram c b0 c b1 c intvcc + c in d1 1 f ceramic m1 m2 m3 m4 d0 + c vin v in r in l1 l0 c out1 v out1 gnd v out0 3874 f07 + c out0 + f in 1 f ceramic tg0 gnd intv cc bg0 boost0 sw0 v in bg1 boost1 sw1 i th1 LTC3874 tg1 i sense1 ? i sense1 + run1 i th0 run0 i sense0 + sync i sense0 ? applications information 3874f ltc 3874
22 for more information www.linear.com/LTC3874 r l1 d1 l1 sw1 v out1 c out1 v in c in r in r l0 d0 bold lines indicate high switching current. keep lines to a minimum length. l0 sw0 3874 f08 v out0 c out0 figure 8. branch current waveforms applications information 3874f ltc 3874
23 for more information www.linear.com/LTC3874 design example as a design example using master controller ltc3866 and slave controller LTC3874 for a 3-phase high current regula - tor, assume v in = 12 v ( nominal), v in = 20 v (maximum), v out = 1.5v, i max = 90a, and f = 400khz (see figure 9). the master controller ltc3866 design can be found in the ltc3866 data sheet design example section. the regulated output voltage is determined by the ltc3866: v out = 0.6v 1 + r b r a ? ? ? ? ? ? using a 20k 1% resistor from the v fb node to ground, the top feedback resistor is ( to the nearest 1% standard value) 30.1k. the frequency is set by biasing the ltc3866 freq pin to 1v . the ltc3866 clkout pin is connected to the LTC3874 sync pin through an inverter. the LTC3874 phasmd pin is connected to 1/3 ? intv cc . the inductance value is based on a 35% maximum ripple current assumption per phase (10.5 a). the highest value of ripple current occurs at the maximum input voltage: l = v out f i l(max) 1? v out v in(max) ? ? ? ? ? ? this design will require 0.33h . the w rth 744301033,0.33 h inductor is chosen for both the ltc3866 and the LTC3874. at the nominal input voltage (12v), the ripple current will be: i l(nom) = v out f l 1? v out v in(nom) ? ? ? ? ? ? it will have 10a (33%) ripple. the peak inductor current will be the maximum dc value plus one-half the ripple current, or 35a. the minimum on-time occurs at the maximum v in , and should not be less than 90ns: t on(min) = v out v in(max) f = 1.5v 20v(400khz) = 187ns dcr current sensing is used in this circuit. for the ltc3866 , if c1 and c2 are chosen to be 220 nf, based on the chosen 0.33h inductor with 0.32 m dcr, r1 and r2 can be calculated as: r1 = l dcr c1 = 4.69k r2 = l dcr c2 5 = 937 choose r1 = 4.64k and r2 = 931 . for the LTC3874, if c3 and c4 are chosen to be 220nf, based on the chosen 0.33 h inductor with 0.32 m dcr, r3 and r4 can be calculated as: r3 = l dcr c3 5 = 937 r4 = l dcr c4 5 = 937 choose r3 = 931 and r4 = 931 . the maximum dcr of the inductor is 0.34 m. the v sense(max) is calculated as: v sense(max) = i peak dcr max = 12mv the current limit is chosen to be 15 mv for the ltc3866. when the current limit is 15 mv for the ltc3866, the i th pin voltage is 2 v. based on table 3, the LTC3874 lowdcr pin is pulled high and the ilim pin is pulled low to choose both channels' current limit to be 14.4 mv when the i th pin voltage is 2v. applications information 3874f ltc 3874
24 for more information www.linear.com/LTC3874 applications information both ics run pins are connected together. during start- up, the ltc3866 has 1 a current to pull up the run pins. a 4.7 nf capacitor is connected to the run pins to ensure the LTC3874 run pins have 4 ms delay after v in is ready . the ltc3866 pgood pin is connected to the LTC3874 fault pins through a nmos switch. the switch is con - trolled by the ltc3866 tk/ss pin. during the soft-start, the switch is off. the LTC3874 fault pins are pulled up by a 120 k resistor. when the soft-start interval is done, the nmos switch is turned on. the LTC3874 fault pins are controlled by the ltc3866 pgood pin. the LTC3874 mode pins are tied to the ltc3866 pgood pin for start-up control. the ltc3866 and LTC3874 choose the same power mosfet, c in , and c out . the power dissipation on the topside mosfet can be easily estimated. choosing an infineon bsc050ne2ls mosfet results in: r ds(on) = 7.1m ( max), v miller = 2.8v, c miller ? 35 pf. at maximum input voltage with tj (estimated) = 75?c: p main = 1.5v 20v (30a) 2 [1 + (0.005)(75 c ? 25 c)] (0.0071 ) + (20v) 2 30a 2 ? ? ? ? ? ? (2 )(35pf) 1 5.5v ? 2.8v + 1 2.8v ? ? ? ? ? ? (400khz) = 599mw + 122mw = 721mw an infineon bsc010ne2ls, r ds(on) = 1.1 m, is chosen for the bottom fet. the resulting power loss is: p sync = 20v ? 1.5v 20v (30a) 2 [1 + (0.005)(75 c ? 25 c)] (0.001 1 ) = 1.14w 3874f ltc 3874
25 for more information www.linear.com/LTC3874 figure 9. high efficiency, triple phase sub-milliohm dcr sensing 1.5v/90a step-down supply applications information freq mode/pllin run 100k 0.1f 220pf 10k 20k ra rb 30.1k pgood tk/ss itemp ith extv cc v in v fb diffout intv cc diffp boost tg diffn snsd + sns ? snsa + pgnd bg sw i lim clkout ltc3866 sgnd 30.1k 120k 2.2 v in 4.5v to 14v 931 r2 r1 4.64k v out 1.5v 90a l1 0.33h dcr = 0.32m gnd 10k 1.5nf c1 220nf c2 220nf 0.1f bsc050ne2ls bsc010ne2ls cmdsh-3 10f 2 100f 6 330f 6 4.7f 1k 2n3904 1f 3874 f09 10f 2 4.7f c4 220nf l3 l2 r4 931 75k 0.1f 0.1f c3 220nf bsc050ne2ls bsc050ne2ls bsc010ne2ls bsc010ne2ls r3 931 0.33h dcr = 0.32m 0.33h dcr = 0.32m extv cc freg LTC3874 i sense0 ? i th0 i th1 i sense1 + i sense1 ? i sense0 + run0 run1 sync fault0 fault1 bg0 sw0 boost0 tg0 tg1 boost1 sw1 bg1 phasmd lowdcr ilim mode0 mode1 gnd v in intv cc 10f 2 1f 10k gnd 20k 120k 2.2 cmdsh-3 cmdsh-3 2n7002 + 10pf l1, l2, l3 = wrth 744301033 4.7nf 3874f ltc 3874
26 for more information www.linear.com/LTC3874 applications information figure 10. high efficiency, 4-phase 1v/120a step-down supply v in intv cc tg2 tg1 boost2 boost1 sw2 sw1 bg1 bg2 tcomp2 phasmd tcomp1 entempb i th1 snsd1 + snsd2 + sns1 ? sns2 ? snsa2 + i th2 vosns1 + run1 run2 vosns2 + vosns1 ? vosns2 ? snsa1 + clkout tk/ss1 tk/ss2 ilim pgood trset2 trset1 mode/pllin tavg ifast freq extv cc ltc3875 sgnd/pgnd 715 715 100k 3.57k 13.3k 20k 100k 4.02k 10k 30.1k gnd 220nf 220nf 3.57k 2.2 cmdsh-3 bsc050ne2ls bsc050ne2ls bsc010ne2lsi v out 1.0v 120a 220nf 220nf 3874 f10 10f 2 4.7f 220nf l1, l2, l3, l4: wrth 744301025 l4 715 75k 0.1f 0.1f 220nf bsc050ne2ls l3 bsc050ne2ls bsc010ne2lsi bsc010ne2lsi 715 0.25h dcr = 0.32m 0.25h dcr = 0.32m extv cc freq LTC3874 i sense0 ? i th0 i th1 i sense1 + i sense1 ? i sense0 + run0 run1 sync fault0 fault1 bg0 sw0 boost0 tg0 tg1 boost1 sw1 bg1 phasmd lowdcr ilim mode0 mode1 gnd v in intv cc 100pf 10f 2 1f gnd 120k 2.2 cmdsh-3 cmdsh-3 2n7002 l1 v in 4.5v to 14v l2 bsc010ne2lsi cmdsh-3 4.7f 0.1f 10f 2 10f 2 0.1f 1f 100f 12 2.2nf 220pf 0.1f 330f 12 0.25h dcr = 0.32m 0.25h dcr = 0.32m + 10nf 3874f ltc 3874
27 for more information www.linear.com/LTC3874 information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no representa- tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. package description please refer to http://www .linear.com/designtools/packaging/ for the most recent package drawings. 4.00 0.10 (2 sides) 2.50 ref 5.00 0.10 (2 sides) note: 1. drawing proposed to be made a jedec package outline mo-220 variation (wxxx-x). 2. drawing not to scale 3. all dimensions are in millimeters 4. dimensions of exposed pad on bottom of package do not include mold flash. mold flash, if present, shall not exceed 0.15mm on any side 5. exposed pad shall be solder plated 6. shaded area is only a reference for pin 1 location on the top and bottom of package pin 1 top mark (note 6) 0.40 0.10 27 28 1 2 bottom view?exposed pad 3.50 ref 0.75 0.05 r = 0.115 typ r = 0.05 typ pin 1 notch r = 0.20 or 0.35 45 chamfer 0.25 0.05 0.50 bsc 0.200 ref 0.00 ? 0.05 (ufd28) qfn 0506 rev b recommended solder pad pitch and dimensions apply solder mask to areas that are not soldered 0.70 0.05 0.25 0.05 0.50 bsc 2.50 ref 3.50 ref 4.10 0.05 5.50 0.05 2.65 0.05 3.10 0.05 4.50 0.05 package outline 2.65 0.10 3.65 0.10 3.65 0.05 ufd package 28-lead plastic qfn (4mm 5mm) (reference ltc dwg # 05-08-1712 rev b) 3874f ltc 3874
28 for more information www.linear.com/LTC3874 ? linear technology corporation 2013 lt 1113 ? printed in usa linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax : (408) 434-0507 www.linear.com/LTC3874 related parts typical application part number description comments ltc3866 single output synchronous step-down dc/dc controller with sub-milliohm dcr sensing pll fixed 250khz to 770khz frequency, 4.5v v in 38v, 0.6v v out 3.5v ltc3774 dual current mode synchronous step-down controller with sub-milliohm dcr sensing operates with power blocks, drmos devices or external drives/mosfets, 4.5v v in 38v, 0.6v v out 3.5v ltc3855 2-phase, dual output synchronous step-down dc/dc controller with differential remote sense pll fixed frequency 250khz to 770khz, 4.5v v in 38v, 0.6v v out 12.5v ltc3833 fast accurate step-down dc/dc controller with differential output sensing very fast transient response, t on( min) = 20ns, 4.5v v in 38v , 0.6v v out 5.5 v, tssop-20e, 3mm 4mm qfn-20 ltc3891 60v, low i q synchronous step-down dc/dc controller pll capable fixed frequency 50khz to 900khz, 4v v in 60v, 0.8v v out 24v, i q = 50a ltc3856 2-phase, single output synchronous step-down dc/dc controller with diff amp and dcr temp compensation pll fixed 250khz to 770khz frequency, 4.5v v in 38v, 0.6v v out 5.25v ltc3829 3-phase, single output synchronous step-down dc/dc controller with diff amp and dcr temp compensation pll fixed 250khz to 770khz frequency, 4.5v v in 38v, 0.6v v out 5.25v ltc3861 dual, multiphase, synchronous step-down dc/dc controller with diff amp and three-state output drive operates with power blocks, drmos devices or external drivers/mosfets, 3v v in 24v, t on(min) = 20ns ltc3869/ ltc3869-2 2-phase, dual output synchronous step-down dc/dc controllers, with accurate multiphase current matching pll fixed frequency 250khz to 780khz, 4v v in 30v, 0.6v v out 12.5v, 4mm 5mm qfn-28, ssop-28 v in 4.7f boost0 sw0 bg0 boost1 tg0 tg1 sw1 bg1 i lim LTC3874 phasmd freq gnd run0 sync run1 fault0 fault1 0.1f 0.1f l1 0.33h (0.32m dcr) l2 0.33h (0.32m dcr) 0.22f 0.22f run0 gpio0 gpio1 run1 sync i th0 i th1 v sense0 + master controller i sense0 + i sense0 ? i sense1 + i sense1 ? i th0 i th1 v sense1 + 931 931 470f 2 470f 2 v out0 1.0v 60a v out1 1.5v 60a l1, l2: wrth 744301033 m1, m2: bsc050ne2ls m3, m4: bsc010ne2ls v out1 v in intv cc extv cc pgood0 pgood1 mode0 mode1 lowdcr + + 90k 3874 ta02 m1 m3 m4 m2 high efficiency dual 1.0v/1.5v step-down converter 3874f ltc 3874

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